The present invention relates to clock synchronization circuitry including a cascaded phase locked loop. In particular the present invention relates to a delay stage for a ring oscillator and a fine phase tuning circuitry, both used in the cascaded phase locked loop.
Clock synchronization in integrated circuits is typically performed by a phase locked loop (PLL).
Some prior PLLs use a ring oscillator as a voltage controlled oscillator. A ring oscillator is a chain of inversion elements coupled together in a negative feedback fashion, with each element contributing a delay amount which adds up to half an oscillation period. Some prior phase locked loop implementations using ring oscillators suffer phase offset and deadband problems, which are difficult to minimize without compromising one or the other.
One disadvantage of prior ring oscillators is that the number of phase signals that can be generated are limited by the number of inversion elements contained in the ring oscillator. The number of inversion elements is, in turn, limited by the length of time delay contributed by each inversion element. The greater the time delay of the inversion element, the fewer the number of inversion elements that can be included in the ring oscillator.
Another disadvantage of some prior oscillators is that they must include an odd number of inversion elements to develop a phase shift of greater than 180xc2x0.
Other prior PLLs use voltage controlled delay line to generate the phase shift necessary for oscillation. Such prior PLLs have a limited delay range, typically a clock period or less. Hence, the frequency of operation of such prior PLLs is very limited. Prior PLLs including delay lines also tend to be susceptible to supply noise because of their use of CMOS inverters, which couple supply noise directly into output signals.
One object of the present invention is to provide a method and circuitry for synchronizing internal device functions to an external clock.
Another object of the present invention is to provide a method and circuitry for clock synchronization that allows phase deadband characteristics to be easily optimized.
Another object of the present invention is to provide a method and circuitry for clock synchronization that allows easy optimization of stability characteristics.
Another object of the present invention is to provide a method and circuitry for clock synchronization that minimizes the affect of the delay of clock buffers.
Another object of the present invention is to provide a method and circuitry for clock synchronization that minimizes the affect of a cock distribution network on loop stability.
A still further object of the present invention is to provide a method and circuitry for clock synchronization that allows easy optimization of loop bandwidth.
A further object of the present invention is to provide a method and circuitry for clock synchronization that provides high rejection of power supply noise.
Another object of the present invention is to provide a method and circuitry for fine phase adjustment with small static phase error and high loop stability.
Another object of the present invention is to provide a method and circuitry for phase adjustment in which there are no boundary conditions or start up conditions to be concerned with.
Another object of the present invention is to provide a method and circuitry for clock synchronization that provides smooth phase adjustment.
Another object of the present invention is to provide a method and circuitry for clock synchronization that is suitable for a wide range of frequencies.
Another object of the present invention is to provide a method and circuitry for clock synchronization that minimizes restart response time after power down.
Another object of the present invention is to provide a method and circuitry for clock synchronization that compensates for the delays associated with data input circuitry and data output circuitry.
A still further object of the present invention is to provide a method and circuitry for clock synchronization that generates an output signal with an controlled phase offset with respect to the input reference signal.
A method of performing phase adjustment in a phase locked loop is described. First, two phase signals are selected from a multiplicity of phase signals. The two selected phase signals are selected by a select signal. Next, an output signal is generated by interpolating between the two selected phase signals. The contribution of each of the two selected phase signals to the output signal is determined by a weighting signal.
Also described is phase tuning circuitry, which includes a phase selector and a phase interpolator. The phase selector selects two phase signals from a multiplicity of phase signals in response to a select signal. The two selected phase signals are coupled to the phase interpolator. The phase interpolator generates an output signal by interpolating between the two selected phase signals. The relative contribution of each of the two selected phase signals to the output signal is determined by a weighting signal.
Also described is a delay stage for a ring oscillator. The ring oscillator includes an even number of cascaded delay stages. Each delay stage includes a differential amplifier, which generates two complementary output signals. Coupled between the complementary output signals, two voltage clamping means limit the peak-to-peak voltage swing of the output signal. Limiting the peak-to-peak voltage swing of the output signal speeds-up the delay stage and allows the ring oscillator to includes a greater number of delay stages.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and the detailed description that follows.